IEEE 2016 VLSI Projects
1.High-Density Shift-Register-Based Rapid Single-Flux-Quantum Memory System for Bit-Serial
Microprocessors
2.Area-Efficient SOT-MRAM With a Schottky Diode
3.2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D
Integration
4.An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay
5.FTCAM: An Area-Efficient Flash-Based Ternary CAM Design
1.Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
2.Design of Efficient Content Addressable Memories in High- Performance FinFET Technology
3.Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
4.Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA
5.Energy Consumption of VLSI Decoders
6.Exact and Approximate Algorithms for the Filter Design Optimization Problem
7.Fast Code Design for Overloaded Code-Division Multiplexing Systems
8.Fine-Grained Access Management in Reconfigurable Scan Networks
9.FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems
10.Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
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